1. Field of the Invention
This invention relates to phase-locked loops and more particularly to calibration circuits therefor.
2. Description of Related Art
Commonly assigned U.S. Pat. No. 5,508,660 of Gersbach et at for a xe2x80x9cCharge Pump Circuit with Symmetrical Current Output for Phase-Controlled Loop Systemxe2x80x9d shows a circuit which includes a charge pump connected between a phase comparator and a Voltage Controlled Oscillator (VCO). The output of the VCO is fed back in a phase-locked loop to the other input of the phase comparator. The phase comparator is connected to the feedback signal from the VCO and a source of a reference signal with a given input frequency. The output of the charge pump circuit is a current which is filtered by an RC filter that produces a control voltage based upon incrementing and decrementing signals received from the phase comparator. The control voltage across the RC filter is supplied to the input of the VCO. It is mentioned that a frequency divider can be interposed between the source of the reference signal, and the comparator, if desired. No means of calibration of the phase-controlled loop system is shown.
Commonly assigned U.S. Pat. No. 5,382,922 of Gersbach et at. for a xe2x80x9cCalibration Systems and Methods for Setting PLL Gain Characteristics and Center Frequencyxe2x80x9d users two comparator inputs from a single filter voltage and performs a single pass calibration. There is a phase comparator connected to a source of a reference signal with a given input frequency. The output of the phase comparator is supplied to the input of a charge pump circuit. The output of the charge pump circuit is a current which is supplied in parallel to a calibration system and an RC filter that produces a control voltage based upon incrementing and decrementing signals from the charge pump. In this case, the output voltage from the filter is supplied to a Voltage-to-Current Converter VCC), the output of which is introduced to a summing node. The control voltage across the RC filter is supplied to the input of a VCO. The output of the VCO is fed back in a phase-locked loop to the other input of the phase comparator. The patent states that a frequency divider can be interposed between the source of the reference signal, and the comparator, if desired. The output of the calibration system is also supplied to the summing node. The output of the summing node is supplied to an oscillator which together with the voltage-to-current converter comprises a VCO. The calibration system includes calibration logic which receives inputs from a pair of comparators and produces an up signal when the control voltage is greater than a second reference voltage and a down signal when the control voltage is less than a first reference voltage. When the calibration cycle has resulted in the xe2x80x9cHigh Order Counter Bits Unchanged For n Cyclesxe2x80x9d, then the xe2x80x9ccalibration complete signal is issued . . . and processing terminates . . . xe2x80x9d That is to say that the calibration is not continuous. The patent also states xe2x80x9cAutomated, repeated calibration of the PLL circuit is anticipated using the integrated, digital circuits described. An optimal voltage-frequency point is attained by the repeated calibration of the PLL to a center, steady state frequency.xe2x80x9d
The problem with the stopping of the cycle of calibration and then automated repeating of the process is that with the systems taught in the prior art, each time the calibration cycle is started, the system cannot handle data because of the jitter of the VCO during the intermittent or one time calibration process.
Commonly assigned U.S. Patent No. 6,175,282 of Yasuda for xe2x80x9cMethod for Calibrating a VCO Characteristic and Automatically Calibrated PLL Having a VCOxe2x80x9d claims calibrating an oscillation frequency versus a control voltage characteristic of a VCO in which an oscillation frequency is changed in responsive to a control voltage, performing a calibration to establish an oscillation frequency in the VCO at a maximum target frequency value when a control input to the VCO reaches a reference voltage, and verifying that the control voltage is within an operating range when the oscillation frequency is established at a minimum target frequency value. The flow chart of the calibration process of Yasuda also ends two steps after the reference frequency is less than the control voltage, at the point at which xe2x80x9cthe oscillation frequency of is actually reduced to the lowest value ft L of the target frequency of the VCO . . . xe2x80x9d, i.e. xe2x80x9cfo=ft_Lxe2x80x9d and the flow chart indicates that the process ends at that point. There is no suggestion of a repetition of the process to maintain continuous calibration.
Additional references include U.S. Pat. No. 5,027,087 of Rottinghans for xe2x80x9cFast-Switching Frequency Synthesizerxe2x80x9d; U.S. Pat. No. 5,625,325 of Rotzoll et al. for xe2x80x9cSystem and Method for Phase Lock Loop Gain Stabilizationxe2x80x9d; U.S. Pat. No. 5,686,864 of Martin et al. for xe2x80x9cMethod and Apparatus for Controlling a Voltage Controlled Oscillator Tuning Range in a Frequency Synthesizerxe2x80x9d; U.S. Pat. No. 5,909,149 of Bath et al. for xe2x80x9cMultiband Phase Locked Loop Using a Switched Voltage Controlled Oscillator; and U.S. Pat. No. 5,942,949 of Wilson et al. for xe2x80x9cSelf-Calibrating Phase-Lock Loop with Auto-Trim Operations for Selecting an Appropriate Oscillator Operating Curvexe2x80x9d.
An object of this invention is to provide a system including a comparator circuit and calibration circuit which solve the problem of having to deal with Voltage Controlled Oscillator (VCO) frequency (xe2x80x9cspeedxe2x80x9d) drift due to temperature, voltage, and other environmental variations during operation. The dynamic nature of the DCC circuit of this invention functions better than static circuits that attempt to compensate for environmental changes.
To solve the problems of such variations, an object of the present invention is to provide a system capable of continuous recalibration of the PLL without causing errors due to jitter.
In accordance with this invention, a calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump receives an error signal from the phase/frequency detector and provides a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive or negative limit. A calibration means for continuously providing incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.
Preferably, the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator. The calibration means begins a calibration cycle by sampling the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time. The calibration means determines whether the calibration has corrected a detected error and repeats the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle.
Preferably the VCO comprises a voltage to current (V-I) converter connected to provide an input to a current controlled oscillator (ICO), and the calibration means includes a Dynamic Course Correction (DCC) circuit and a Digital to Analog Converter (DAC) and the DAC provides an input to the ICO.
Preferably, the DAC includes means delaying the rate of change of incremental calibration input to the ICO.
BIST Built-In Self Test
CALCOMP Calibration Comparators System including a set of three analog comparators that lock at the differential filter voltage from the FILTER and produce three digital outputs DIFF_HI, DIFF_LO and DIFF_POS.
CALCOMPS_PD Signal source is Analog. The signal powers down the CALCOMP system 20 by going high for all but 80 of the 31,250 cycles between sampling of the DIFF_HI, DIFF_LO, and DIFF_POS inputs (75 cycles before and 5 afterwards), Disables the CALCOMP system 20 when a logic xe2x80x9c1xe2x80x9d.
CC_COMP Signal source is Corecntl. The signal indicates that VCOCTL macro circuit has completed the first calibration when high, i.e. when a logic xe2x80x9c1xe2x80x9d it denotes that the first coarse calibration has been completed.
CC_COUNT(8:0) Signal sources are Analog and Corecntl This is the six bit coarse calibration count value. Zero is the least significant bit. This calibration count value is converted in the IDAC 24 (FIG. 1) to a current.
CC_ERROR Signal source is Corecntl; Denotes if there is a calibration error., i.e. when a logic xe2x80x9c1xe2x80x9d it denotes that an error has occurred, either CC_COUNT less than xe2x80x9c0xe2x80x9d, or CC_COUNT greater than all xe2x80x9c1""sxe2x80x9d was attempted
CORECNTL Optional logic designed into chip to operate and/or test VCOCTL macro.
DCC Dynamic Coarse Calibration Circuit containing digital logic that implements the state diagrams shown in FIGS. 7 and 8
DIFF_HI Signal source is Analog. This signal tells the VCOCTL macro circuit to increment the CC_COUNT. Note, should not be high when DIFF_POS is low. It has a logic xe2x80x9c1xe2x80x9d value when xc2xd* (Filter+xe2x88x92Filterxe2x88x92) greater than 250 mV
DIFF_LO Signal source is Analog. This signal tells the VCOCTL macro circuit to decrement the CC_COUNT. Note, should not be high when DIFF_POS is high. It has a logic xe2x80x9c1xe2x80x9dvalue when xc2xd* (Filter+xe2x88x92Filterxe2x88x92) less than xe2x88x92250 mV
DIFF_POS Signal source is Analog. This signal tells the VCOCTL macro circuit when the VCO differential control voltage passes the zero point of the desired frequency. It is high when there is a positive control voltage and low when there is a negative control voltage It has a logic xe2x80x9c1xe2x80x9d value when Filter+ greater than Filterxe2x88x92
DLPF Differential Low Pass Filter
DYNAMIC-EN Signal source is External. When this signal provides a logicxe2x80x9c1xe2x80x9d, it enables the dynamic coarse calibration mode, whereas when this signal provides a logic xe2x80x9c0xe2x80x9d, it enables single pass operation.
FILTER Differential low pass filter of the up and down charge current inputs supplied by the charge pump (Q-pump) Single-ended filter designs can also be used.
FILTP (Filter+) Positive (+) output from the low pass filter
FILTN (Filterxe2x88x92) Negative (xe2x88x92) output from the low pass filter
FREQ_OUT (fo) Output frequency of VCO (fo): fo=fref* N
FREQ_REF (fref) Reference frequency than is N times smaller than Freq. Out: fref=fo/N
IDAC I (Current) Digital to Analog Converter 24 (FIG. 1)
INCC Signal source is from Corecntl. This signal increments the CC_COUNT by one (used for dynamic mode testing). Used for testing in a laboratory environment. When transitioning from a logic xe2x80x9c0xe2x80x9d to a logic xe2x80x9c1xe2x80x9d, it increases the CC_COUNT output by a logic xe2x80x9c1xe2x80x9d.
LSSD xe2x80x9cLevel Sensitive Scan Designxe2x80x9d as described in commonly assigned Gregor U.S. Pat. No. 6,304,122 for xe2x80x9cLow Power LSSD Flip Flops and a Flushable Single Clock Splitter for Flip Flopsxe2x80x9d.
LSSDA Signal source is from Corecntl, LSSDA is a positive active clock. When TESTMODE is high, this input is used to clock the logic. When TESTMODE is low, this clock is forced low.
LSSDB Signal source is from Corecntl, LSSDB is also a positive active clock. When TESTMODE is low, this clock is forced high
LSSDC Signal source is from Corecntl, LSSDC is also a positive active clock. As with LSSDB, when TESTMODE is high, this input is used to clock the logic. When TESTMODE is low, this clock is forced high.
N Positive integer which is the division value of the phase lock loop frequency divider
P/F DETECT Phase/Frequency Detector compares fo/N to fref.
If fo/N greater than fref, then an up pulse is given.
If fo/N less than fref, then a down pulse is given.
If fo and fref are equal, then either both up and down pulses or neither are given.
PLL Phase Locked Loop
PWRDWN Powers down the DCC circuit when the signal is a logic xe2x80x9c1xe2x80x9d. This signal is used in applications implemented with multiple DCC circuits and one may want to shut off idle DCC units to save power.
Q-PUMP Charge pump that either adds charge when an up signal is given or takes away charge when a down signal is given.
REFCLK Internal reference clock in DCC which is used to drive internal latches in DCC This is typically the system clock which is used to drive the DCC logic state machine that executes the single or dynamic operations.
RESET Reset signal that sets CC_COMP, CC_ERROR, and all CC_COUNT bits to xe2x80x9c0xe2x80x9d
SCANGATE Signal source is Corecntl. When SCANGATE is high, the LSSD clocks are used instead of the system clocks. This is used during manufacturing test to check for stuck faults. SCANGATE is low in normal operation and during module BIST testing.
SCANIN Signal source is Corecntl, LSSD scan data input.
REFCLK Signal source is External. This is the 33.3 MHz reference clock from the analog partition.
RESET Signal from Corecntl, the signal resets the state of the VCOCTL macro circuit when high.
SCANOUT Corecntl LSSD scan data output.
SLUMBER Link, when SLUMBER goes high, the VCOCTL macro circuit enters the slumber power mode (slumber state) and stays there until a set intervalxcx9c1600 xcexcs after SLUMBER goes low.
V+ xc2xd* (Filter++Filterxe2x88x92)+250 mV
Vxe2x88x92 xc2xd* (Filter++Filterxe2x88x92)xe2x88x92250 mV
VCOCTL macro circuit for controlling VCO frequency